The present invention relates, generally, to an improved circuit and method for frequency acquisition and, more particularly, to a self trimming circuit and method for frequency acquisition and clock recovery.
Generally, all communication systems include a transmitter, a receiver and a communication channel. A fiber optic communication system is a lightwave system employing optical fibers as the communication medium. Optical fibers transport the optical signal (lightwave) with relatively little power loss. Power or fiber loss is largely due in part to noise or jitter in the signal. Signal noise can be caused by many different sources, such as, for example, thermal noise, shot noise and imperfect fiber.
Power loss consideration is an important design parameter. In particular, the power loss determines the repeater spacing of a long-haul lightwave system. During normal signal transmission it is necessary to periodically regenerate the optical signal with a repeater. Repeater stations include an optical receiver-transmitter pair that detects the incoming optical signal, recovers the electrical bit stream, and converts it back to an optical bit stream by modulating the transmission. The optical receiver portion typically consists of a digital optical receiver. The digital optical receiver includes a clock and data recovery (CDR) component comprising a decision circuit and a clock recovery circuit.
In a typical repeater, the decision circuit first compares the output from the channel to a threshold level at a sampling time determined by the clock-recovery circuit. Next, the decision circuit decides whether the signal corresponds to bit xe2x80x9c1xe2x80x9d or bit xe2x80x9c0.xe2x80x9d
The purpose of the clock-recovery circuit is to isolate a spectral component at a frequency (f) equal to the bit rate (B) from the received signal. This component provides information about the bit slot to the decision circuit and helps to synchronize the bit sampling process. In the case of RZ (return-to-zero) format, a spectral component at f=B is present in the received signal and a narrow bandpass filter such as a surface-acoustic-wave (SAW) filter can effectively isolate this component. Clock recovery is more difficult in the case of NRZ (non-return-to-zero) format because the received signal lacks a spectral component at f=B. NRZ is the standard data format in SONET (synchronous optical network) systems and SONET is the standard for the telecommunications industry.
The CDR circuit restores and retimes the NRZ bit sequence by extracting the clock signal from the received data. Because the spectrum of a NRZ random bit sequence does not have a spectral component at the bit rate f=B, this spectral component has to be created using nonlinear signal processing. The component at f=B is generated, filtered and phase aligned to the NRZ data to yield a clock signal. In general, a phase and frequency locked loop (PFLL) is used to perform both the filtering and the phase alignment. The incoming data is resampled with a clean clock to filter, for example, jitter present on the data.
The clean clock is provided by a voltage controlled oscillator (VCO). The frequency and phase of the NRZ data controls the input voltage to the VCO in a loop configuration. The VCO frequency and phase are adjusted in response to the input NRZ data frequency and phase. Ideally, the VCO free running frequency (i.e., without control from the loop) should be as close as possible to the frequency of the incoming data. However, in an integrated CDR, the VCO free running frequency can vary considerably from the data frequency (e.g., up to a xc2x150% difference). In fact, the data frequency may be outside the maximum frequency tuning range of the VCO or outside the maximum range of the frequency detector. In both cases, it is very difficult for the loop configuration to effectively adjust the VCO frequency to the data frequency.
The CDR generally has two loops: a phase loop to clean up and lock the phase; and a frequency loop to adjust the VCO frequency to the incoming data frequency. Referring now to FIG. 1, an exemplary schematic of a two loop CDR of the prior art is shown. As illustrated, CDR 100 comprises a phase loop 102, a frequency loop 104, a VCO 106, and a frequency window 112. Phase loop 102 includes a phase detector 108. Phase detector 108 has a very narrow frequency range and, therefore, the VCO frequency must be close to the incoming data frequency for the phase loop to lock. Frequency loop 104 includes a frequency detector 110 having a wider frequency acquisition range than phase loop 102, typically around plus or minus twenty five percent (xc2x125%) if working with no external reference. Frequency loop 104 receives the incoming NRZ data when the CDR system is initialized.
Frequency detector 110 can be a frequency detector (FD) such as the Pottbxc3xa4cker frequency detector. Referring now to FIG. 2, the Pottbxc3xa4cker FD 200 includes a phase detector (PD) 202, a quadrature phase detector (QPD) 204, a frequency detector (FD) 206, and an output 208. It should be noted that output 208 is averaged by a low pass filter 210. In fact, the output of frequency detector 110 and phase detector 108 of FIG. 1 are also averaged by low pass filter (LPF2) and (LPF1) respectively. In PD 202 and QPD 204, the VCO signal is sampled by the NRZ input signal. The two beat notes (Q1 and Q2 of FD 206) are subsequently processed in FD 206. The output 208 is the average of Q3. For a complete understanding of the Pottbxc3xa4cker FD, refer to: A. Pottbxc3xa4cker, U. Langmann, and H. -U. Schreiber, xe2x80x9cAn 8 Gb/s Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s,xe2x80x9d IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, December 1992, the disclosure of which is incorporated herein by reference.
Referring again to FIG. 1, frequency detector 110 changes the frequency of VCO 106 using the incoming data frequency as the reference. The incoming data frequency is compared to the VCO frequency by frequency detector 110. If the incoming data frequency is higher than the VCO frequency, frequency detector 110 will output a positive average and the frequency of VCO 106 will be driven higher. Conversely, if the data frequency is lower than the VCO frequency, the average will be negative and the frequency of VCO 106 will be driven lower.
The change of VCO 106 frequency continues until the frequency of VCO 106 nears the incoming data frequency (e.g., typically around xc2x11% difference). Frequency window 112 is a counter that monitors the frequencies of loop 104 comparing the frequencies of the beat between the incoming data and the VCO, namely, the output of PD 202 or QPD 204 of FIG. 2. Once the frequencies approach an acceptably low difference, frequency window 112 sends a signal to shut off loop 104 causing a switch coupled to the input of VCO 106 to engage phase loop 102.
The frequency acquisition range of frequency detector 110 is wider than the range of phase detector 108, however the range is nonetheless limited. The VCO free running frequency must lie within approximately xc2x125% of the output of frequency detector 110 for loop 104 to effectively change the VCO frequency. However, in operation the difference between the VCO frequency and the bit rate (B) can be as high as xc2x150%.
Referring now to FIG. 3, an exemplary averaged output (e.g., output 208 after low pass filter 210) of a conventional.(e.g., Pottbxc3xa4cker) frequency detector is shown. For exemplary purposes only, the frequency is illustrated as varying from zero to twice the incoming data frequency. As we know, NRZ format lacks a spectral component at f=B. As shown in, FIG. 3, a change of sign in average occurs at 2500 (2.5 GHz) representing the spectral component at f=B. Thus, 2500 is the center frequency or the desired lock point in the exemplary output of FIG. 3. Under ideal conditions, the VCO frequency will be the centered frequency and lock at the zero average point.
If the VCO free running frequency is 3000 (above the 0 average), the averaged output of the frequency detector will be set negative and the VCO frequency will be driven lower towards 2500, as expected. On the other hand, if the free running frequency is 2000 (below the 0 average), the averaged output will be set positive and the VCO frequency will be driven higher towards 2500, again as expected. However, if the free running frequency is 1000 the output is set negative and the VCO frequency will be driven lower, away from the desired center frequency (2500). Similarly, at a VCO frequency of 4000 the output is set positive and the VCO frequency will be subsequently increased away from 2500. Thus, unless the VCO is xe2x80x9ctunedxe2x80x9d (frequency range limited) to a frequency in the range of the desired center frequency and within the frequency detector""s limited acquisition range, the frequency loop can not properly modulate the VCO and the CDR will not function. Furthermore, the VCO can lock on less dramatic spikes or drops which do not represent the center frequency.
One technique used in the industry includes an external reference clock having a nominal operating frequency at the desired clock frequency. The frequency detector receives an external reference clock, such as a crystal oscillator, instead of the incoming NRZ data. The VCO frequency is divided and compared with the crystal oscillator frequency.
The external crystal is very precise but allows little room for deviation from the desired frequency. Once the crystal frequency is chosen, the CDR circuit operates only at that bit rate and multiples of that frequency until the crystal is replaced with a different crystal at a different frequency. Thus, for variable-bit rate CDRs, the external crystal lacks the flexibility of multiple frequencies. In fact, to operate a truly variable bit rate CDR with the external crystal technique requires additional crystals which must be changed, thereby increasing the circuit process time and cost.
A second prior art technique includes a post-production trimming of the VCO frequency until the frequency is within the frequency detector""s acquisition range. Fuses are burned onto each chip to trim either the bias current of the VCO or the capacitance on the VCO, depending upon the architecture of the circuit. Alternatively, each chip can be laser-trimmed by machine but this method increases production costs. Post-production trimming requires careful chip by chip processing, making this technique both expensive and time consuming.
Accordingly, there exists a need for an improved circuit and method for wide range frequency acquisition of NRZ data. More particularly, there is a need for a flexible CDR circuit that can accommodate multiple bit rates without significantly increasing production time or costs.
The present invention overcomes the problems of the prior art and provides an improved CDR circuit and method for recovering the clock from NRZ data. In particular, the present invention provides a start-up loop for self-trimming the VCO frequency. More particularly, the CDR circuit and method of a preferred embodiment tunes the VCO by sweeping the VCO frequency to detect the desired center frequency.
In a preferred embodiment, a CDR circuit comprises a conventional two loop architecture of the phase and frequency loops plus a third trimming loop. The trimming loop includes a ramp generator for modifying the VCO frequency. The VCO frequency is tuned to a workable frequency range of a conventional frequency detector with no external reference.
In one embodiment the trimming loop includes a decision circuit to monitor the averaged digital output from the frequency detector. When the output registers a long series of positives to negatives, the decision circuit generates a pulse to shut off the trimming loop. The remaining frequency and phase loops are engaged. The VCO is trimmed to within the frequency detector""s acquisition range with limited expense and time.